1. Field of the Invention
The present invention relates to a semiconductor memory integrated circuit(IC), and more particularly to a semiconductor memory IC in which semiconductor memory ICs having the same circuit configuration and pad arrangement can be packaged into different types of IC packages.
2. Description of Related Art
Even though conventional semiconductor memory integrated circuits(ICs) generally share the same configuration, they may have a different pad structure, depending on the form or type of IC package in which they are to be packaged.
For example, a semiconductor memory IC which is packaged into a thin small outline package (TSOP) and a semiconductor memory IC which is packaged into a ball grip array (BGA) will have a different pad arrangement from each other.
FIG. 1 shows an X16 TSOP semiconductor memory device which employs a conventional semiconductor memory IC.
In FIG. 1, reference numeral 10 represents a TSOP semiconductor memory device, reference numeral 12 represents a semiconductor memory IC in the TSOP semiconductor memory device, reference numeral 12-1 represents data input/output (IO) pads in the semiconductor memory IC (which can be implemented as an X36 semiconductor memory device), and reference numeral 12-2 represents address and instruction pads in the semiconductor memory IC. “DQ” represents data IO pins, and “ADD” and “CMD” represent address and instruction pins.
As can be seen in FIG. 1, pads of the semiconductor memory IC 12 of the conventional TSOP semiconductor memory device 10 are arranged on left and right sides of the data IO pads 12-1 and the address and instruction pads 12-2, respectively. Also, the corresponding data IO pins DQ, and the address and instruction pins ADD and CMD, are similarly arranged on left and right sides of the conventional TSOP semiconductor memory device 10.
FIG. 2 shows an X36 BGA package semiconductor memory device which employs a conventional semiconductor memory IC.
In FIG. 2, reference numeral 20 represents a BGA package semiconductor memory device. Like reference numerals of FIGS. 1 and 2 denote like components. “1DQ” represents first data IO (input/output) balls, “ADD” and “CMD” represent address and instruction balls, and “2DQ” represents second data IO balls.
As can be seen in FIG. 2, the first data IO balls 1DQ are positioned at a left side of the package, the address and instruction balls ADD and CMD are positioned at a central portion of the package, and the second data IO balls 2DQ are arranged at a right portion of the package. Here, of 36 data IO balls, the first data IO balls 1DQ represent 18 data IO balls, and the second data IO balls 2DQ represent the rest 18 data IO balls.
Therefore, in the case where the semiconductor memory IC having the same circuit configuration and pad arrangement as that shown in FIG. 1 is packaged into the X36 BGA package semiconductor memory device, the wire bonding process is not straightforward, because the distance between the data IO pads 12-1 and the second data IO balls 2DQ is too far, and thus failure of the semiconductor memory device is more likely due to improper wire bonding.
It is thus impossible to manufacture the semiconductor memory IC 12 to have a circuit configuration and pad arrangement that is similar in arrangement to, and therefore compatible with, the layout of both the X16 TSOP and X36 BGA semiconductor device packages. For this reason, in this example, there is a disadvantage in that a semiconductor memory IC having a pad arrangement for the X36 BGA package semiconductor memory device should be separately manufactured.
In view of the above, in a conventional semiconductor memory IC, it is difficult, if not impossible, to package a semiconductor memory IC having the same circuit configuration and pad arrangement into different types of semiconductor memory device packages having a different number of data IO pins, or a different layout of data IO pins, without the need for re-manufacturing the semiconductor memory IC.